The present invention relates to an information processing system which includes a smart memory group having an arithmetic and logical function.
Recently, the integration density of a memory chip or CPU (namely, central processing unit) chip has been increased year after year, and a high integration density, which was unattainable in the past, is now being realized. Accordingly, the information transmitting speed of the memory chip or the information processing speed of CPU chip has been greatly improved. However, the improvement in the access speed to the memory chip has been too slight to correspond to the above-mentioned improvement in integration density.
In order to solve this problem, two methods can be considered. In one of the methods, a high-speed memory is included in a host CPU chip. In a second method, a large-capacity external memory is formed of a smart memory which has a small-scale arithmetic and logical function, to act as a co-processor. According to the second method, part of the arithmetic and logical processing carried out by the host CPU chip can be distributed to the co-processor, and thus the number of accesses between the host CPU and the external memory can be reduced. In a case where the external memory is formed of a smart memory, however, it is impossible to make the function level of the co-processor (that is, the external memory) equal to the function level of the host CPU, since that circuit part of the co-processor, which is used for the arithmetic and logical processing, is far smaller in scale than a similar circuit part of the host CPU. Accordingly, there arises a problem that the host CPU and the co-processor use different instruction sets. This problem can be solved by using a subset of the instruction set of the host CPU as the instruction set of the co-processor. However, it is necessary to make the circuit scale of the co-processor for arithmetic and logical processing as small as possible, and it is required that the co-processor can be coupled to various kinds of host CPU's. Accordingly, the host CPU and the co-processor are obliged to use different instruction sets. Thus, the host CPU issues instructions to each of the co-processors in an instruction word (that is, a machine word) which is exclusively used in the co-processor, and data is transferred between the host CPU and the co-processor in the above instruction word.
A concept common to two units having different instruction sets is usually expressed by a high level language. In a case where a program written in a high level language is executed between two host CPU's having different instruction sets, the contents of the program are executed one by one, with the aid of an interpreter dedicated to each host CPU, or the program is translated by a compiler and then executed. In this case, however, it is necessary to construct the interpreter or compiler for each CPU, and it takes a long time to construct the interpreter or compiler. Further, the interpreter is slow in operation speed. In view of the above facts, an improved method shown in FIG. 1 has been devised, in which an intermediate language is used. Referring to FIG. 1, a high level language 100 is compiled by an intermediate language output compiler 101 into an intermediate language 102, and thus an intermediate language code string is formed. An intermediate language compiler (or interpreter) 120 for a CPU 121 and an intermediate language compiler (or interpreter) 130 for a CPU 131, which are usually called a code generator, are constructed to convert the intermediate language code string into two kinds of instruction code strings, each of which is exclusively used in and executed by a corresponding one of the CPU's 121 and 131. Accordingly, it is required that the intermediate language is easy to produce and can be readily converted into a desired machine word. Further, the intermediate language output compiler 101 for converting the high level language 100 into the intermediate language is written in the intermediate language, and is converted by a code generator 110 into an instruction code string, which is exclusively used in and executed by the CPU 121 or 131. According to the method shown in FIG. 1, a time necessary to construct compilers 120 and 130 for the CPU's 121 and 131 can be made as short as possible, and the instruction code string formed by each compiler can be executed at high speed. The above method using the intermediate language, however, is usually based upon an assumption that the CPU's are equal in function level to each other, and hence is not usually used between a host CPU and a co-processor, which have largely different function levels from each other.